/*
 * Copyright (c) 2021 MediaTek Inc.
 *
 * Use of this source code is governed by a MIT-style
 * license that can be found in the LICENSE file or at
 * https://opensource.org/licenses/MIT
 */

#pragma once

/* PMIC Registers for regulator */
#define MT6330_VEFUSE_ANA_CON0               0x1e98
#define MT6330_VEFUSE_ANA_CON1               0x1e99
#define MT6330_LDO_VEFUSE_CON0               0x1b87
#define MT6330_LDO_VEFUSE_MON                0x1b8a

/* PMIC Registers for keys */
#define MT6330_TOPSTATUS                     0x18
#define MT6330_PSC_TOP_INT_STATUS0           0x915

/* PMIC Registers for PSC */
#define MT6330_SWCID0                        0xa
#define MT6330_TOP_RST_MISC0                 0x136
#define MT6330_PPCCTL0                       0xa08
#define MT6330_PPCCTL1                       0xa09
#define MT6330_STRUP_CON4                    0xa15
#define MT6330_STRUP_CON12                   0xa0f

/* PMIC Registers for AUXADC */
#define MT6330_AUXADC_DSN_ANA_ID             0x1000
#define MT6330_AUXADC_DSN_DIG_ID             0x1001
#define MT6330_AUXADC_DSN_ANA_REV            0x1002
#define MT6330_AUXADC_DSN_DIG_REV            0x1003
#define MT6330_AUXADC_DSN_DBI                0x1004
#define MT6330_AUXADC_DSN_ESP                0x1005
#define MT6330_AUXADC_DSN_FPI                0x1006
#define MT6330_AUXADC_DSN_DXI                0x1007
#define MT6330_AUXADC_ANA_CON0               0x1008
#define MT6330_AUXADC_ANA_CON1               0x1009
#define MT6330_AUXADC_ANA_CON2               0x100a
#define MT6330_AUXADC_ANA_CON3               0x100b
#define MT6330_AUXADC_ANA_CON4               0x100c
#define MT6330_AUXADC_ANA_CON5               0x100d
#define MT6330_AUXADC_ANA_CON6               0x100e
#define MT6330_AUXADC_ELR_NUM                0x100f
#define MT6330_AUXADC_ELR_0                  0x1010
#define MT6330_AUXADC_ELR_1                  0x1011
#define MT6330_AUXADC_ELR_2                  0x1012
#define MT6330_AUXADC_DIG_1_DSN_ANA_ID       0x1080
#define MT6330_AUXADC_DIG_1_DSN_DIG_ID       0x1081
#define MT6330_AUXADC_DIG_1_DSN_ANA_REV      0x1082
#define MT6330_AUXADC_DIG_1_DSN_DIG_REV      0x1083
#define MT6330_AUXADC_DIG_1_DSN_DBI          0x1084
#define MT6330_AUXADC_DIG_1_DSN_ESP          0x1085
#define MT6330_AUXADC_DIG_1_DSN_FPI          0x1086
#define MT6330_AUXADC_DIG_1_DSN_DXI          0x1087
#define MT6330_AUXADC_ADC0_L                 0x1088
#define MT6330_AUXADC_ADC0_H                 0x1089
#define MT6330_AUXADC_ADC1_L                 0x108a
#define MT6330_AUXADC_ADC1_H                 0x108b
#define MT6330_AUXADC_ADC2_L                 0x108c
#define MT6330_AUXADC_ADC2_H                 0x108d
#define MT6330_AUXADC_ADC3_L                 0x108e
#define MT6330_AUXADC_ADC3_H                 0x108f
#define MT6330_AUXADC_ADC4_L                 0x1090
#define MT6330_AUXADC_ADC4_H                 0x1091
#define MT6330_AUXADC_ADC5_L                 0x1092
#define MT6330_AUXADC_ADC5_H                 0x1093
#define MT6330_AUXADC_ADC6_L                 0x1094
#define MT6330_AUXADC_ADC6_H                 0x1095
#define MT6330_AUXADC_ADC7_L                 0x1096
#define MT6330_AUXADC_ADC7_H                 0x1097
#define MT6330_AUXADC_ADC8_L                 0x1098
#define MT6330_AUXADC_ADC8_H                 0x1099
#define MT6330_AUXADC_ADC9_L                 0x109a
#define MT6330_AUXADC_ADC9_H                 0x109b
#define MT6330_AUXADC_ADC10_L                0x109c
#define MT6330_AUXADC_ADC10_H                0x109d
#define MT6330_AUXADC_ADC11_L                0x109e
#define MT6330_AUXADC_ADC11_H                0x109f
#define MT6330_AUXADC_ADC14_L                0x10a0
#define MT6330_AUXADC_ADC14_H                0x10a1
#define MT6330_AUXADC_ADC15_L                0x10a2
#define MT6330_AUXADC_ADC15_H                0x10a3
#define MT6330_AUXADC_ADC16_L                0x10a4
#define MT6330_AUXADC_ADC16_H                0x10a5
#define MT6330_AUXADC_ADC17_L                0x10a6
#define MT6330_AUXADC_ADC17_H                0x10a7
#define MT6330_AUXADC_ADC18_L                0x10a8
#define MT6330_AUXADC_ADC18_H                0x10a9
#define MT6330_AUXADC_ADC19_L                0x10aa
#define MT6330_AUXADC_ADC19_H                0x10ab
#define MT6330_AUXADC_ADC20_L                0x10ac
#define MT6330_AUXADC_ADC20_H                0x10ad
#define MT6330_AUXADC_ADC21_L                0x10ae
#define MT6330_AUXADC_ADC21_H                0x10af
#define MT6330_AUXADC_ADC22_L                0x10b0
#define MT6330_AUXADC_ADC22_H                0x10b1
#define MT6330_AUXADC_ADC23_L                0x10b2
#define MT6330_AUXADC_ADC23_H                0x10b3
#define MT6330_AUXADC_ADC24_L                0x10b4
#define MT6330_AUXADC_ADC24_H                0x10b5
#define MT6330_AUXADC_ADC26_L                0x10b6
#define MT6330_AUXADC_ADC26_H                0x10b7
#define MT6330_AUXADC_ADC27_L                0x10b8
#define MT6330_AUXADC_ADC27_H                0x10b9
#define MT6330_AUXADC_ADC30_L                0x10ba
#define MT6330_AUXADC_ADC30_H                0x10bb
#define MT6330_AUXADC_ADC32_L                0x10bc
#define MT6330_AUXADC_ADC32_H                0x10bd
#define MT6330_AUXADC_ADC33_L                0x10be
#define MT6330_AUXADC_ADC33_H                0x10bf
#define MT6330_AUXADC_ADC34_L                0x10c0
#define MT6330_AUXADC_ADC34_H                0x10c1
#define MT6330_AUXADC_ADC37_L                0x10c2
#define MT6330_AUXADC_ADC37_H                0x10c3
#define MT6330_AUXADC_ADC38_L                0x10c4
#define MT6330_AUXADC_ADC38_H                0x10c5
#define MT6330_AUXADC_ADC39_L                0x10c6
#define MT6330_AUXADC_ADC39_H                0x10c7
#define MT6330_AUXADC_ADC40_L                0x10c8
#define MT6330_AUXADC_ADC40_H                0x10c9
#define MT6330_AUXADC_ADC_NTCT0_L            0x10ca
#define MT6330_AUXADC_ADC_NTCT0_H            0x10cb
#define MT6330_AUXADC_ADC_NTCT1_L            0x10cc
#define MT6330_AUXADC_ADC_NTCT1_H            0x10cd
#define MT6330_AUXADC_ADC_NTCT2_L            0x10ce
#define MT6330_AUXADC_ADC_NTCT2_H            0x10cf
#define MT6330_AUXADC_ADC_NTCT3_L            0x10d0
#define MT6330_AUXADC_ADC_NTCT3_H            0x10d1
#define MT6330_AUXADC_ADC_EXT0_L             0x10d2
#define MT6330_AUXADC_ADC_EXT0_H             0x10d3
#define MT6330_AUXADC_ADC_EXT1_L             0x10d4
#define MT6330_AUXADC_ADC_EXT1_H             0x10d5
#define MT6330_AUXADC_ADC41_L                0x10d6
#define MT6330_AUXADC_ADC41_H                0x10d7
#define MT6330_AUXADC_ADC42_L                0x10d8
#define MT6330_AUXADC_ADC42_H                0x10d9
#define MT6330_AUXADC_ADC43_L                0x10da
#define MT6330_AUXADC_ADC43_H                0x10db
#define MT6330_AUXADC_ADC44_L                0x10dc
#define MT6330_AUXADC_ADC44_H                0x10dd
#define MT6330_AUXADC_ADC46_L                0x10de
#define MT6330_AUXADC_ADC46_H                0x10df
#define MT6330_AUXADC_ADC45_L                0x10e0
#define MT6330_AUXADC_ADC45_H                0x10e1
#define MT6330_AUXADC_ADC47_L                0x10e2
#define MT6330_AUXADC_ADC47_H                0x10e3
#define MT6330_AUXADC_ADC48_L                0x10e4
#define MT6330_AUXADC_ADC48_H                0x10e5
#define MT6330_AUXADC_ADC49_L                0x10e6
#define MT6330_AUXADC_ADC49_H                0x10e7
#define MT6330_SDMADC_ADC0_L                 0x10e8
#define MT6330_SDMADC_ADC0_H                 0x10e9
#define MT6330_AUXADC_STA0                   0x10ea
#define MT6330_AUXADC_STA1                   0x10eb
#define MT6330_AUXADC_STA2                   0x10ec
#define MT6330_AUXADC_STA3                   0x10ed
#define MT6330_AUXADC_STA4                   0x10ee
#define MT6330_AUXADC_STA5                   0x10ef
#define MT6330_SDMADC_STA0                   0x10f0
#define MT6330_AUXADC_DIG_2_DSN_ANA_ID       0x1100
#define MT6330_AUXADC_DIG_2_DSN_DIG_ID       0x1101
#define MT6330_AUXADC_DIG_2_DSN_ANA_REV      0x1102
#define MT6330_AUXADC_DIG_2_DSN_DIG_REV      0x1103
#define MT6330_AUXADC_DIG_2_DSN_DBI          0x1104
#define MT6330_AUXADC_DIG_2_DSN_ESP          0x1105
#define MT6330_AUXADC_DIG_2_DSN_FPI          0x1106
#define MT6330_AUXADC_DIG_2_DSN_DXI          0x1107
#define MT6330_AUXADC_RQST0                  0x1108
#define MT6330_AUXADC_RQST1                  0x1109
#define MT6330_AUXADC_RQST2                  0x110a
#define MT6330_AUXADC_RQST3                  0x110b
#define MT6330_AUXADC_RQST4                  0x110c
#define MT6330_SDMADC_RQST0                  0x110d
#define MT6330_AUXADC_DIG_3_DSN_ANA_ID       0x1180
#define MT6330_AUXADC_DIG_3_DSN_DIG_ID       0x1181
#define MT6330_AUXADC_DIG_3_DSN_ANA_REV      0x1182
#define MT6330_AUXADC_DIG_3_DSN_DIG_REV      0x1183
#define MT6330_AUXADC_DIG_3_DSN_DBI          0x1184
#define MT6330_AUXADC_DIG_3_DSN_ESP          0x1185
#define MT6330_AUXADC_DIG_3_DSN_FPI          0x1186
#define MT6330_AUXADC_DIG_3_DSN_DXI          0x1187
#define MT6330_AUXADC_CON0                   0x1188
#define MT6330_AUXADC_CON1                   0x1189
#define MT6330_AUXADC_SPL_CON0               0x118a
#define MT6330_AUXADC_SPL_CON1               0x118b
#define MT6330_AUXADC_SPL_CON2               0x118c
#define MT6330_AUXADC_SPL_CON3               0x118d
#define MT6330_AUXADC_SPL_CON4               0x118e
#define MT6330_AUXADC_SPL_CON5               0x118f
#define MT6330_AUXADC_SPL_CON6               0x1190
#define MT6330_AUXADC_SPL_CON7               0x1191
#define MT6330_AUXADC_SPL_CON8               0x1192
#define MT6330_AUXADC_AVG_CON0               0x1193
#define MT6330_AUXADC_AVG_CON1               0x1194
#define MT6330_AUXADC_AVG_CON2               0x1195
#define MT6330_AUXADC_AVG_CON3               0x1196
#define MT6330_AUXADC_AVG_CON4               0x1197
#define MT6330_AUXADC_AVG_CON5               0x1198
#define MT6330_AUXADC_AVG_CON6               0x1199
#define MT6330_AUXADC_AVG_CON7               0x119a
#define MT6330_AUXADC_AVG_CON8               0x119b
#define MT6330_AUXADC_TRIM_CON0              0x119c
#define MT6330_AUXADC_TRIM_CON1              0x119d
#define MT6330_AUXADC_TRIM_CON2              0x119e
#define MT6330_AUXADC_TRIM_CON3              0x119f
#define MT6330_AUXADC_TRIM_CON4              0x11a0
#define MT6330_AUXADC_TRIM_CON5              0x11a1
#define MT6330_AUXADC_TRIM_CON6              0x11a2
#define MT6330_AUXADC_CON28                  0x11a3
#define MT6330_AUXADC_CON29                  0x11a4
#define MT6330_AUXADC_CON30                  0x11a5
#define MT6330_AUXADC_CON31                  0x11a6
#define MT6330_AUXADC_CON32                  0x11a7
#define MT6330_AUXADC_CON33                  0x11a8
#define MT6330_AUXADC_CON34                  0x11a9
#define MT6330_AUXADC_CON35                  0x11aa
#define MT6330_AUXADC_CON36                  0x11ab
#define MT6330_AUXADC_CON37                  0x11ac
#define MT6330_AUXADC_CON38                  0x11ad
#define MT6330_AUXADC_CON39                  0x11ae
#define MT6330_AUXADC_CON40                  0x11af
#define MT6330_AUXADC_CON41                  0x11b0
#define MT6330_AUXADC_CON42                  0x11b1
#define MT6330_AUXADC_CON43                  0x11b2
#define MT6330_AUXADC_CON44                  0x11b3
#define MT6330_AUXADC_CON45                  0x11b4
#define MT6330_AUXADC_AUTORPT0               0x11b5
#define MT6330_AUXADC_AUTORPT1               0x11b6
#define MT6330_AUXADC_AUTORPT2               0x11b7
#define MT6330_AUXADC_ACCDET0                0x11b8
#define MT6330_AUXADC_ACCDET1                0x11b9
#define MT6330_AUXADC_DBG0                   0x11ba
#define MT6330_AUXADC_DBG1                   0x11bb
#define MT6330_AUXADC_DBG2                   0x11bc
#define MT6330_SDMADC_CON0                   0x11bd
#define MT6330_SDMADC_CON1                   0x11be
#define MT6330_SDMADC_CON2                   0x11bf
#define MT6330_SDMADC_CON3                   0x11c0
#define MT6330_AUXADC_DIG_3_ELR_NUM          0x11c1
#define MT6330_AUXADC_DIG_3_ELR0             0x11c2
#define MT6330_AUXADC_DIG_3_ELR1             0x11c3
#define MT6330_AUXADC_DIG_3_ELR2             0x11c4
#define MT6330_AUXADC_DIG_3_ELR3             0x11c5
#define MT6330_AUXADC_DIG_3_ELR4             0x11c6
#define MT6330_AUXADC_DIG_3_ELR5             0x11c7
#define MT6330_AUXADC_DIG_3_ELR6             0x11c8
#define MT6330_AUXADC_DIG_3_ELR7             0x11c9
#define MT6330_AUXADC_DIG_3_ELR8             0x11ca
#define MT6330_AUXADC_DIG_3_ELR9             0x11cb
#define MT6330_AUXADC_DIG_3_ELR10            0x11cc
#define MT6330_AUXADC_DIG_3_ELR11            0x11cd
#define MT6330_AUXADC_DIG_3_ELR12            0x11ce
#define MT6330_AUXADC_DIG_3_ELR13            0x11cf
#define MT6330_AUXADC_DIG_3_ELR14            0x11d0
#define MT6330_AUXADC_DIG_3_ELR15            0x11d1
#define MT6330_AUXADC_DIG_3_ELR16            0x11d2
#define MT6330_AUXADC_DIG_3_ELR17            0x11d3
#define MT6330_AUXADC_DIG_3_ELR18            0x11d4
#define MT6330_AUXADC_DIG_3_ELR19            0x11d5
#define MT6330_AUXADC_DIG_3_ELR20            0x11d6
#define MT6330_AUXADC_DIG_3_ELR21            0x11d7
#define MT6330_AUXADC_DIG_3_ELR22            0x11d8
#define MT6330_AUXADC_DIG_3_ELR23            0x11d9
#define MT6330_AUXADC_DIG_3_ELR24            0x11da
#define MT6330_AUXADC_DIG_3_ELR25            0x11db
#define MT6330_AUXADC_DIG_3_ELR26            0x11dc
#define MT6330_AUXADC_DIG_3_ELR27            0x11dd
#define MT6330_SDMADC_DIG_3_ELR28            0x11de
#define MT6330_SDMADC_DIG_3_ELR29            0x11df
#define MT6330_SDMADC_DIG_3_ELR30            0x11e0
#define MT6330_SDMADC_DIG_3_ELR31            0x11e1
#define MT6330_SDMADC_DIG_3_ELR32            0x11e2
#define MT6330_SDMADC_DIG_3_ELR33            0x11e3
#define MT6330_SDMADC_DIG_3_ELR34            0x11e4
#define MT6330_SDMADC_DIG_3_ELR35            0x11e5
#define MT6330_AUXADC_DIG_3_ELR36            0x11e6
#define MT6330_AUXADC_DIG_3_ELR37            0x11e7
#define MT6330_AUXADC_DIG_3_ELR38            0x11e8
#define MT6330_AUXADC_DIG_3_ELR39            0x11e9
#define MT6330_AUXADC_DIG_3_ELR40            0x11ea
#define MT6330_AUXADC_DIG_3_ELR41            0x11eb
#define MT6330_AUXADC_DIG_3_ELR42            0x11ec
#define MT6330_AUXADC_DIG_3_ELR43            0x11ed
#define MT6330_AUXADC_DIG_3_ELR44            0x11ee
#define MT6330_AUXADC_DIG_3_ELR45            0x11ef
#define MT6330_AUXADC_DIG_3_ELR46            0x11f0
#define MT6330_AUXADC_DIG_3_ELR47            0x11f1
#define MT6330_AUXADC_DIG_3_ELR48            0x11f2
#define MT6330_AUXADC_DIG_3_ELR49            0x11f3
#define MT6330_AUXADC_DIG_3_ELR50            0x11f4
#define MT6330_AUXADC_DIG_3_ELR51            0x11f5
#define MT6330_AUXADC_DIG_3_ELR52            0x11f6
#define MT6330_AUXADC_DIG_3_ELR53            0x11f7
#define MT6330_AUXADC_DIG_3_ELR54            0x11f8
#define MT6330_AUXADC_DIG_3_ELR55            0x11f9
#define MT6330_AUXADC_DIG_4_DSN_ANA_ID       0x1200
#define MT6330_AUXADC_DIG_4_DSN_DIG_ID       0x1201
#define MT6330_AUXADC_DIG_4_DSN_ANA_REV      0x1202
#define MT6330_AUXADC_DIG_4_DSN_DIG_REV      0x1203
#define MT6330_AUXADC_DIG_4_DSN_DBI          0x1204
#define MT6330_AUXADC_DIG_4_DSN_ESP          0x1205
#define MT6330_AUXADC_DIG_4_DSN_FPI          0x1206
#define MT6330_AUXADC_DIG_4_DSN_DXI          0x1207
#define MT6330_AUXADC_IMP0                   0x1208
#define MT6330_AUXADC_IMP1                   0x1209
#define MT6330_AUXADC_IMP2                   0x120a
#define MT6330_AUXADC_IMP3                   0x120b
#define MT6330_AUXADC_IMP4                   0x120c
#define MT6330_AUXADC_LBAT0                  0x120d
#define MT6330_AUXADC_LBAT1                  0x120e
#define MT6330_AUXADC_LBAT2                  0x120f
#define MT6330_AUXADC_LBAT3                  0x1210
#define MT6330_AUXADC_LBAT4                  0x1211
#define MT6330_AUXADC_LBAT5                  0x1212
#define MT6330_AUXADC_LBAT6                  0x1213
#define MT6330_AUXADC_LBAT7                  0x1214
#define MT6330_AUXADC_LBAT8                  0x1215
#define MT6330_AUXADC_LBAT9                  0x1216
#define MT6330_AUXADC_LBAT10                 0x1217
#define MT6330_AUXADC_LBAT11                 0x1218
#define MT6330_AUXADC_LBAT2_0                0x1219
#define MT6330_AUXADC_LBAT2_1                0x121a
#define MT6330_AUXADC_LBAT2_2                0x121b
#define MT6330_AUXADC_LBAT2_3                0x121c
#define MT6330_AUXADC_LBAT2_4                0x121d
#define MT6330_AUXADC_LBAT2_5                0x121e
#define MT6330_AUXADC_LBAT2_6                0x121f
#define MT6330_AUXADC_LBAT2_7                0x1220
#define MT6330_AUXADC_LBAT2_8                0x1221
#define MT6330_AUXADC_LBAT2_9                0x1222
#define MT6330_AUXADC_LBAT2_10               0x1223
#define MT6330_AUXADC_LBAT2_11               0x1224
#define MT6330_AUXADC_BAT_TEMP_0             0x1225
#define MT6330_AUXADC_BAT_TEMP_1             0x1226
#define MT6330_AUXADC_BAT_TEMP_2             0x1227
#define MT6330_AUXADC_BAT_TEMP_3             0x1228
#define MT6330_AUXADC_BAT_TEMP_4             0x1229
#define MT6330_AUXADC_BAT_TEMP_5             0x122a
#define MT6330_AUXADC_BAT_TEMP_6             0x122b
#define MT6330_AUXADC_BAT_TEMP_7             0x122c
#define MT6330_AUXADC_BAT_TEMP_8             0x122d
#define MT6330_AUXADC_BAT_TEMP_9             0x122e
#define MT6330_AUXADC_BAT_TEMP_10            0x122f
#define MT6330_AUXADC_BAT_TEMP_11            0x1230
#define MT6330_AUXADC_BAT_TEMP_12            0x1231
#define MT6330_AUXADC_THR0                   0x1232
#define MT6330_AUXADC_THR1                   0x1233
#define MT6330_AUXADC_THR2                   0x1234
#define MT6330_AUXADC_THR3                   0x1235
#define MT6330_AUXADC_THR4                   0x1236
#define MT6330_AUXADC_THR5                   0x1237
#define MT6330_AUXADC_THR6                   0x1238
#define MT6330_AUXADC_THR7                   0x1239
#define MT6330_AUXADC_THR8                   0x123a
#define MT6330_AUXADC_THR9                   0x123b
#define MT6330_AUXADC_THR10                  0x123c
#define MT6330_AUXADC_THR11                  0x123d
#define MT6330_AUXADC_MDRT_0                 0x123e
#define MT6330_AUXADC_MDRT_1                 0x123f
#define MT6330_AUXADC_MDRT_2                 0x1240
#define MT6330_AUXADC_MDRT_3                 0x1241
#define MT6330_AUXADC_MDRT_4                 0x1242
#define MT6330_AUXADC_MDRT_5                 0x1243
#define MT6330_AUXADC_DCXO_MDRT_0            0x1244
#define MT6330_AUXADC_DCXO_MDRT_1            0x1245
#define MT6330_AUXADC_DCXO_MDRT_2            0x1246
#define MT6330_AUXADC_NAG_0                  0x1247
#define MT6330_AUXADC_NAG_1                  0x1248
#define MT6330_AUXADC_NAG_2                  0x1249
#define MT6330_AUXADC_NAG_3                  0x124a
#define MT6330_AUXADC_NAG_4                  0x124b
#define MT6330_AUXADC_NAG_5                  0x124c
#define MT6330_AUXADC_NAG_6                  0x124d
#define MT6330_AUXADC_NAG_7                  0x124e
#define MT6330_AUXADC_NAG_8                  0x124f
#define MT6330_AUXADC_NAG_9                  0x1250
#define MT6330_AUXADC_NAG_10                 0x1251
#define MT6330_AUXADC_NAG_11                 0x1252
#define MT6330_AUXADC_NAG_12                 0x1253
#define MT6330_AUXADC_NAG_13                 0x1254
#define MT6330_AUXADC_NAG_14                 0x1255
#define MT6330_AUXADC_NAG_15                 0x1256
#define MT6330_AUXADC_NAG_16                 0x1257
#define MT6330_AUXADC_NAG_17                 0x1258
#define MT6330_AUXADC_NAG_18                 0x1259
#define MT6330_AUXADC_RSV_0                  0x125a
#define MT6330_AUXADC_RSV_1                  0x125b
#define MT6330_AUXADC_SPL_LIST_0             0x125c
#define MT6330_AUXADC_SPL_LIST_1             0x125d
#define MT6330_AUXADC_SPL_LIST_2             0x125e
#define MT6330_AUXADC_SPL_LIST_3             0x125f
#define MT6330_AUXADC_SPL_LIST_4             0x1260

